The list of Rivlan's projects includes:
and circtuit design of a fast CMOS ADC and
DAC in 65 nm technology. Sampling rate 2 Gbps, ENOB - 6.5 bits for DAC and 6.0 bit for
- Design of LDO in CMOS 90
nm technology. Regulated
voltage 1.2 V, current 400 mA. Low dropout voltage of 190
mV. Low output noise of 0.2 µV/vHz.
and circuit design for an 8 GHz VCO in an advanced submicron CMOS
process. Main challenge was delivering a stringent phase-noise
spec, while complying with a very low critical breakdown voltage.
design of a zero-IF DVB-H tuner. Balance of system level IIP3,
IIP2 and noise performance. Designing the individual block
specs. Review of the block performance with respect to the
system spec. Mentoring the block designers in order to improve
the overall performance.
and circuit design for a Si-Ge BiCMOS
AGC-less IF-strip consisting of gm-C
filters and gain blocks for a zero-IF data receiver.
study for system and circuit design of a CMOS universal
analog/DTV/cable TV tuner. Both low-IF and zero-IF
architectures have been evaluated and designed. Fixed-video
(ATSC, DVB-T, ISDB-T, NTSC, PAL), cable (DVB-C, DOCSIS) and
mobile-video (DVB-H, ISDB-T) tuners have been initially
designed and tested. Six patent applications have been
filled, 4 patents have been granted and 2 more patent
applications are still pending.
design and test procedure for RF wafer-probe test structures for all
fundamental block of a 2.4/5.7 GHz 802.11 transceiver in Si-Ge BiCMOS technology. The blocks included LNA,
down-mixer, VCO, divider, up-mixer and driver amplifier.
BiCMOS and straight CMOS block versions have been designed and its
performance evaluated and compared.
and circuit design for BiCMOS continuous-time real and complex gm-C IF- filters
for GPS low-IF receiver.
and circuit design for a CMOS W-CDMA IF-channel consisting of
receive and transmit parts.
Implementation of VGAs, mixers, phase shifters, on-chip VCO
and PLL. Two patents applied for and granted jointly with
and circuit design for a bipolar GPS receiver consisting of LNA,
mixer, VGAs, AGC and PLL.
study for the design of a CMOS 900 MHz ISM-band transmitter with
on-chip VCO and power amplifier.
BiCMOS implementation for a PCS/AMPS
handset receiver RF front-end including LNAs, mixers, switches and
study for system and circuit design for a CDMA receiver CMOS RF front-end
consisting of LNA, mixers and IF amplifier.